1. Field of the Invention
The invention relates to a method of fabricating an integrated circuit and more particularly to a method of fabricating a dynamic random access memory (DRAM) and an embedded DRAM.
2. Description of the Related Art
DRAM is a volatile memory, and the way to store digital signals is decided by charge or discharge of the capacitor in the DRAM. Therefore, when the power applied on the DRAM is turned off, the data stored in the memory cell completely disappears. One DRAM cell includes one field effect transistor (FET) and one capacitor. The capacitor is used to store the signals in the cell of DRAM. If more charges can be stored in the capacitor, the capacitor has less interference when the data is sensed by the amplifier.
FIG. 1 is a schematic, cross sectional view of a DRAM known in prior art. A memory region 100 and a periphery circuit region 102 are defined on a substrate 104. A word line 106 is formed on the substrate 104 in the memory region 100 and a gate 108 is simultaneously formed in the periphery circuit region 102. A source/drain region (not shown) is formed beside the gate 108 and the word line 106, such that a FET is formed in the periphery circuit region 100. A bit line 112 is then formed within a dielectric layer 110, which covers the word line 106 and gate 108. Dielectric layers 114, 118 are formed on the dielectric layer 110 and a capacitor 116 in the memory region 100 is formed therein. A contact 120 window in the periphery circuit region 102 is then formed by etching through the dielectric layers 118, 114. 112 and 110, and the depth of the contact window 120 is about 20000.ANG.. A conductive layer then fills the contact window 120 to form a contact 122, and wiring lines 124 are formed on the dielectric layer 118 by circuitry layout.
As the dimension of the semiconductor device is reduced, an aspect ratio of the contact window 120 in the periphery circuit region 102 is therefore increased. The contact window 120 is too deep to cause difficulty for etching the dielectric layer 118, 114 and 110, and the dielectric layer 118, 114 and 110 may be not etched through. Thus the source/drain region (no shown) in the periphery circuit region 102 can not be completely exposed and a conductive layer subsequently deposited can not electrically connect to the source/drain region.
In addition, it is hard to deposit the conductive layer to fill the contact window 120 with a high aspect ratio and the performance of the device is therefore reduced.
The problem for etching the contact window in the periphery circuitry region of DRAM is also occurred in the logic circuitry region of an embedded DRAM. The aspect ratio of the contact window in the logic circuitry region is so high, such that the etching process to form the contact window is difficult to perform.
Otherwise, the material of the upper electrode and the lower electrode of the capacitor 116 is polysilicon layer. A depletion region is often produced between the polysilicon layer serving as electrodes and the capacitor dielectric layer due to compensation of electrons and holes. The thickness of the capacitor dielectric layer is therefore increased to cause charge storage decreasing and the performance of the capacitor is reduced.